A Flexible, Technology Adaptive Memory Generation Tool

Memories are by far the most dominating circuit structure found in modern day application specific integrated circuits (ASIC) and system-on-chips (SoC). When considering efficiency, it is not deemed good practice to create different memories from scratch for every unique ASIC. In an era where technology is ever improving and constantly changing, there is a need for versatile and technology adaptive memory generators. There are innumerable types of memory designs; in industry, large teams are often devoted to elaborate custom memory designs. This is generally not possible in academia, as resources and funds are limited, and tight deadlines push for simpler, scalable and customizable memory architectures. This session discusses a design flow methodology for developing a memory generator capable of handling different memory designs and scaling across technology nodes. A highly automated flow, utilizing the power of Cadence SKILL scripting, allows for smaller teams to generate dense and efficient memory designs, as would be useful in academia. A generator is introduced for a .18um technology, developed in 4 to 6 weeks, and is capable of being ported to different technologies by simply changing some technology specific parameters in the scripting. Participants will learn how to incorporate their custom tailored circuits into this automated design flow, making this tool highly customizable. Additionally they will learn to use Cadence Abstract Generator and RTL Compiler to incorporate this memory into a synthesized design flow using Cadence Encounter. This methodology elicits a fast time-to-fabrication, customizable, reproducible and affordable solution for memory generation.